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AS8202B ttp-c2nf communication controller www.ams.com revision 1.0 1 - 20 1 general description the AS8202B communication controller is an integrated device supporting serial communication according to the ttp specification version 1.1. it performs all communication tasks such as reception and transmission of messages in a ttp cluster without interaction of the host cpu. ttp provides mechanisms that allow the deployment in high-dependability distributed real-time systems. it provides the following services: ?? predictable transmission of messages with minimal jitter ?? fault-tolerant distributed clock synchronization ?? consistent membership service with small delay ?? masking of single faults 2 key features ?? dual-channel controller for redundant data transfers ?? dedicated controller supporting ttp (time-triggered protocol class c standardi zed in sae 6003) ?? suited for dependable distributed real-time systems with guaranteed response time ?? asynchronous data rate up to 4 mbit/s (mfm/manchester) ?? synchronous data rate 20 to 25 mbit/s ?? bus interface (speed, encoding) for each channel selectable independently ?? 40 mhz oscillator clock support ?? 16 mhz bus guardian clock with support for 16 mhz crystal or 16 mhz oscillator ?? single power supply 3.3v, 0.35m cmos process ?? full automotive temperature range (-40oc to 125oc) ?? 16k x 16 sram for message, status, control area (communication network interface) and for scheduling information (medl) ?? 4k x 16 (plus parity) instruction code ram for protocol execution code ?? datasheet conforms to protocol revision 2.05 ?? 16k x 16 instruction code rom containing startup execution code and deprecated protocol code revision 1.00 ?? 16-bit non-multiplexed asynchronous host cpu interface ?? 16-bit risc architecture ?? software tools, design support, development boards available visit www.tttech.com ?? certification support package according to rtca/do-254 dal a available ? visit www.tttech.com ?? rohs conform 3 applications the device is ideal for application fields such as, aerospace according to do-254 level a (e.g. flight control, power distribution, engine control), industrial systems, and railway systems. figure 1. block diagram bus guardi an bus guardian ttp bus unit synchronous bus interface (mii) asynchronous bus interface (mfm/ manchester) test interface ttp protocol processor core communication network interface (cni) instruction memory ram & rom d[15:0] a[11:0] ceb oeb web readyb intb led[2:0] ram_clk_testse use_ram_clk xin0 resetb 40 mhz clock host processor interface rxd[1:0] rxclk[1:0] rxdv[1:0] rxer[1:0] xin1 xout1 txd[1:0] cts[1:0] ram_clk_testse ftest stest fidis ttest test interface ttp bus media drivers AS8202B txclk[1:0]
www.ams.com revision 1.0 2 - 20 AS8202B datasheet - applications contents 1 general description ............................................................................................................................... ................................... 1 2 key features ............................................................................................................................... ............................................. 1 3 applications ............................................................................................................................... ............................................... 1 4 pin assignments ............................................................................................................................... ........................................ 3 4.1 pin descriptions ............................................................................................................................... .................................................... 3 5 absolute maximum ratings ............................................................................................................................... ....................... 6 6 electrical characteristics ............................................................................................................................... ........................... 7 7 detailed description ............................................................................................................................... .................................. 9 7.1 host cpu interface ............................................................................................................................... ............................................... 9 7.1.1 synchronous readyb generation .......................................................................................... ................................................. 12 7.2 reset and oscillator ............................................................................................................................... ............................................ 13 7.2.1 external reset signal .................................................................................................. .............................................................. 13 7.2.2 integrated power-on reset .............................................................................................. ......................................................... 13 7.2.3 oscillator circuitry ................................................................................................... ................................................................... 13 7.2.4 built-in characteristics ............................................................................................... ................................................................ 14 7.3 ttp bus interface ............................................................................................................................... ............................................... 14 7.4 ttp asynchronous bus interface ............................................................................................................................... ....................... 15 7.5 ttp synchronous bus interface ............................................................................................................................... ......................... 15 7.6 test interface ............................................................................................................................... ....................................................... 16 7.7 led signals ............................................................................................................................... ........................................................ 16 8 package drawings and markings ............................................................................................................................... ............ 17 9 ordering information ............................................................................................................................... ................................ 19
www.ams.com revision 1.0 3 - 20 AS8202B datasheet - pin assignments 4 pin assignments figure 2. pin assignments (top view) 4.1 pin descriptions table 1. pin descriptions pin name pin number dir description vdd 4, 12, 29, 49, 59, 74 power pin positive power supply vss 13, 30, 41, 50, 60, 75, 80 negative power supply vddbg 70 positive power supply for bus guardian (connect to vdd) vssbg 73 negative power supply for bus guardian (connect to vss) ceb vss vddbg d15 d14 d13 d12 readyb xin1 vssbg web oeb d11 d10 d9 d8 vdd ttest vss xout1 vss vdd a3 a4 vss fidis xin0 nc ctest txd0 vdd cts0 rxer0 txclk0 rxclk0 rxd0 rxdv0 vdd txd1 vss cts1 rxer1 txclk1 rxclk1 rxd1 rxdv1 d7 d5 d6 d4 d2 d3 d1 d0 vdd a10 a11 a9 a7 a8 a6 vss a5 resetb vss intb vdd nc led1 led2 led0 use_ram_clk nc a0 a1 a2 1 20 21 40 41 60 61 80 ftest oscmode stest ram_clk_testse AS8202B ttp communications controller (top view)
www.ams.com revision 1.0 4 - 20 AS8202B datasheet - pin assignments ram_clk_testse 21 ttl input with internal weak pull-down ram_clk when stest=0 and use_ram_clk=1, else test input, connect to vss if not used stest 22 test input, connect to vss ftest 24 test input, connect to vss fidis 25 test input, connect to vss ttest 61 ttl input with internal weak pull-up test input, connect to vdd use_ram_clk 34 ttl input with internal weak pull-down ram_clk pin enable, connect to vss if not used xin0 2 analog cmos pin main clock: 40mhz external clock input ctest 3 test input, to be unconnected oscmode 23 ttl input with internal weak pull-down connect to vdd 1 xin1 72 analog cmos pin bus guardian clock: analog cmos oscillator input, use as input when providing external clock xout1 71 bus guardian clock: analog cmos oscillator output, leave open when providing external clock resetb 26 ttl input with internal weak pull-up main reset input, active low txd0 5 ttl output with internal weak pull-up at tristate ttp bus channel 0: transmit data cts0 6 ttl output with internal weak pull-down at tristate ttp bus channel 0: transmit enable rxd0 11 ttl input with internal weak pull-up ttp bus channel 0: receive data txclk0 7 ttl input with internal weak pull-down ttp bus channel 0: transmit clock (mii mode) rxer0 8 ttl input with internal weak pull-up ttp bus channel 0: receive error (mii mode) rxclk0 9 ttl input with internal weak pull-down ttp bus channel 0: receive clock (mii mode) rxdv0 10 ttl input with internal weak pull-up ttp bus channel 0: receive data valid (mii mode) txd1 14 ttl output with internal weak pull-up at tristate ttp bus channel 1: transmit data cts1 15 ttl output with internal weak pull-down at tristate ttp bus channel 1: transmit enable rxd1 20 ttl input with internal weak pull-up ttp bus channel 1: receive data txclk1 16 ttl input with internal weak pull-down ttp bus channel 1: transmit clock (mii mode) rxer1 17 ttl input with internal weak pull-up ttp bus channel 1: receive error (mii mode) rxclk1 18 ttl input with internal weak pull-down ttp bus channel 1: receive clock (mii mode) rxdv1 19 ttl input with internal weak pull-up ttp bus channel 1: receive data valid (mii mode) table 1. pin descriptions pin name pin number dir description
www.ams.com revision 1.0 5 - 20 AS8202B datasheet - pin assignments a[11:0] 48-42, 39-35 ttl input host interface (cni) address bus 2 d[15:0] 69-62, 58-51 ttl input/output with tristate host interface (cni) data bus, tristate ceb 76 ttl input with internal weak pull-up host interface (cni) chip enable, active low oeb 77 host interface (cni) output enable, active low web 78 host interface (cni) write enable, active low readyb 79 ttl output with internal weak pull-up at tristate host interface (cni) transfer finish signal, active low, open drain 3 intb 28 host interface (cni) time signal (interrupt), active low, open drain led[2:0] 33-31 ttl output with internal weak pull-down at tristate configurable generic output port nc 1, 27, 40 not connected, leave open 1. this pin selects a clock multiplier of 1. this is the only supported operation mode. 2. the device is addressed at 16-bit data word boundaries. if the device is connected to a cpu with a byte-granular address bus, remem- ber that a[11:0] of the AS8202B device has to be connected to a[12:1] of the cpu (considering a little endian cpu address bus) 3. at de-assertion readyb is driven to the inactive value (high) for a configurable time. table 1. pin descriptions pin name pin number dir description
www.ams.com revision 1.0 6 - 20 AS8202B datasheet - absolute maximum ratings 5 absolute maximum ratings stresses beyond those listed in table 2 may cause permanent damage to the device. these are stress ratings only. functional operation of the device at these or any other conditions beyond those indicated in electrical characteristics on page 7 is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. table 2. absolute maximum ratings symbol parameter min max unit notes electrical parameters v dd dc supply voltage -0.3 5.0 v v in input voltage -0.3 v dd +0.3 v any pin i in input current -100 100 ma any pin, t amb =25oc electrostatic discharge esd electrostatic discharge 1000 v hbm: 1kv mil.std.883, method 3015.7 temperature ranges and storage conditions t strg storage temperature -55 +150 oc t body package body temperature 260 oc the reflow peak soldering temperature (body temperature) specified is in accordance with ipc/jedec j-std-020 ?moisture/reflow sensitivity classification for non-hermetic solid state surface mount devices?. the lead finish for pb-free leaded packages is matte tin (100% sn). h humidity non-condensing 5 85 % msl moisture sensitivity level 3 represents a maximum floor life time of 168h
www.ams.com revision 1.0 7 - 20 AS8202B datasheet - electrical characteristics 6 electrical characteristics t amb = -40 to +125 oc, v dd = 3v to +3.6v, v ss = 0v unless otherwise specified. table 3. electrical characteristics symbol parameter conditions min typ max unit operating conditions i dds static supply current all inputs tied to v dd /v ss , clocks stopped, exclusive of i/o drive requirements, v dd =3.6v 5900a i dd operating supply current (see note 1) vdd=3.3v, exclusive of i/o drive requirements 100 ma clk1 clock period of bus guardian clock (see note 1) 62.5 ns ttl input pins and ttl bidirectional pins in input/tristate model v il input low voltage 0.8 v v ih input high voltage 2.0 v i inleak input leakage current pins without pad resistors, v dd =3.6v -1 1 a i il input low current pins with pull-down resistors, v dd =3.0v v in =0.4v 4.9 (see note 2) a v in =0.8v 8.8 (see note 2) pins with pull-up resistors v dd =3.6v v in =0v -15 -75 i ih input high current pins with pull-down resistors v dd =3.6v v in =3.6v 15 75 a pins with pull-up resistors, v dd =3.0v v in =2.0v -10.7 (see note 2) v in =2.5v -6 (see note 2) c in input capacitance 4.5 (see note 2) pf rxd pin t asym_rx t(v in =0.5*v dd ) asymmetric receiver delay rxd t=125oc, v dd =3.0v, c load =35pf rxd[1,0] -2 (see note 3) 2 (see note 3) ns cmos inputs (xin) , drive from external clock generator drive at xin c xin input capacitance 1.9 2.5 pf i xin input current 1 (see note 3) a v il_xin input low voltage 0 0.3* v dd v v ih_xin input high voltage 0.7* v dd v dd v outputs and ttl bi-directional pins in output mode i ol output low current v dd =3.0v, vo = 0.4v -4 ma i oh output high current v dd =3.0v, vo = 2.5v 4 ma
www.ams.com revision 1.0 8 - 20 AS8202B datasheet - electrical characteristics notes: 1. typical values: clk0=40 mhz (duty cycle 45-55%), clk1=16 mhz. 2. implicitly tested. 3. guaranteed by design; not tested during production. i oz output tristate current v dd =3.6v 10 (see note 3) a t rise t(v out =0.1*v dd ) to t(v out =0.9*v dd ) transition time ? rise t = 125 oc, v dd =3.0v, c load =35pf cts[1,0], led[2:0], intb 8.1 (see note 2) ns d[15:0], readyb 8.9 (see note 2) t fall t(v out =0.9*v dd ) to t(v out =0.1*v dd ) transition time ? fall t = 125 oc, v dd =3.0v, c load =35pf cts[1,0], led[2:0], intb 6 (see note 2) ns d[15:0], readyb 7 (see note 2) txd pins t rise t(v out =0.3*v dd ) to t(v out =0.7*v dd ) transition time ? rise txd t = 125 oc, v dd =3.0v, c load =35pf txd[1,0] 4.5 (see note 3) ns t fall t(v out =0.7*v dd ) to t(v out =0.3*v dd ) transition time ? fall txd t = 125 oc, v dd =3.0v, c load =35pf txd[1,0] 3 (see note 3) ns t asym_rx t(v out =0.5*v dd ) asymmetric driver delay txd t = 125 oc, v dd =3.0v, c load =35pf txd[1,0] -3 (see note 3) 3 (see note 3) ns table 3. electrical characteristics symbol parameter conditions min typ max unit
www.ams.com revision 1.0 9 - 20 AS8202B datasheet - detailed description 7 detailed description the AS8202B is the first ttp controller to support both mfm and manchester coding. manchester coding is important for dc-free d ata transmission, which allows the use of transformers in the data stream. the AS8202B is pin-compatible with its predecessor, the as8202. the AS8202B provides support for fault-tolerant, high-speed bus systems in a single device. the communication controller is qualifi ed for the full temperature range required for automotive applications and is certifiable according to rtca standards. it offers superior relia bility and supports data transfer rates of 25 mbit/s with mii and up to 4 mbit/s with mfm/manchester. the cni (communication network interface) forms a temporal firewall. it de-couples the controller network from the host subsyst em by use of a dual ported ram (cni). this prevents the propagation of control errors. the interface to the host cpu is implemented as a 16-bi t wide non- multiplexed asynchronous bus interface. the ttp follows a conflict-free media access strategy called time division multiple access (tdma). this means, ttp deploys a ti me slot technique based on a global time that is permanently synchronized. each node is assigned a time slot in which it is allowed to perform transmit operation. the sequence of time slots is called tdma round, a se t of tdma rounds forms a cluster cycle. the operation of the ne twork is repeated after one cluster cycle. the sequence of interactions forming the cluster cycle is defined in a static time schedule, called message descriptor list (medl). the definition of the medl in conjunction with the global time determines the response time for a servi ce request. the membership of all nodes in the network is evaluated by the communications controller. this information is presented to all correct cluster members in a consistent fashion. during operation, the status of all other nodes is propagated within one tdma round. please re ad more about ttp and request the ttp specification at www.tttech.com . 7.1 host cpu interface the host cpu interface, also referred to as cni (communication network interface), connects the application circuitry to the as 8202b ttp controller. all related signal pins provide an asynchronous read/write access to a dual ported ram located in the AS8202B. ther e are no setup/ hold constraints referring to the microtick (main clock ?clk0?). all accesses have to be executed on a granularity of 16-bit (2 byte), the device does not support byte-wide accesses. the pin a 0 (lsb) of the device differentiates even and odd 16-bit word addresses and is typically connected to a1 of a little-endian host cpu. the a0 o f host cpu is not connected to the device, and the application/driver on the host cpu should force all accesses to be 16-bit. for efficiency reas ons, the host cpu application/driver may access some memory locations of the AS8202B using wider accesses (e.g. 32-bit), and the bus interface of the host cpu will automatically split the access into two consecutive 16-bit wide accesses to the ttp controller. note that particularly in such a setup all timing parameters of the host cpu interface must be met, especially the inactivity timeouts described as symbols 16?19. the host interface features an interrupt or time signal intb to notify the application circuitry of programmed and protocol-spe cific, synchronous and asynchronous events. the host cpu interface allows access to the internal instruction code memory. this is required for proper loading of the protoc ol execution code into the internal instruction code ram, for extensive testing of the instruction code ram and for verifying the instruction cod e rom contents. intb is an open-drain output, i.e. the output is only driven to '0' and is weak-pull-up at any other time, so external pull-up resi stors or transistors may be necessary depending on the application. readyb is also an open-drain output, but with a possibility to be driven to ?1? for a defined time (selectable by register) before we ak-pull-up at any other time. the led port is software-configurable to automatically show some protocol-related states and events, see below for the led port config uration. table 4. host interface ports pin name mode width comment a[11:0] in 12 cni address bus, 12-bit (a0 is lsb) d[15:0] inout (tri) 16 cni data bus, 16-bit (d0 is lsb) ceb in 1 cni chip enable, active low web in 1 cni write enable, active low oeb in 1 cni output enable, active low readyb out (open drain) 1 cni ready, active low intb out (open drain) 1 cni interrupt, time signal, active low ram_clk_testse in 1 host clock use_ram_clk in 1 host clock pin enable
www.ams.com revision 1.0 10 - 20 AS8202B datasheet - detailed description asynchronous readyb permits the shortest possible bus cycle but eventually requires signal synchronization in the application. connect use_ram_clk to vss to enable this mode of operation. synchronous readyb uses an external clock (usually the host processor?s bus clock) for synchronization of the signal, eliminating external synchronization logic. connect use_ram_clk to vdd and ram_clk_t estse to the host processor's bus clock to enable this mode of operation. note: due to possible metastability occurrence, it is not recommended to be used in safety critical systems. table 5. asynchronous dpram interface symbol parameter conditions min typ max units tc controller cycle time 25 ns 1a input valid to ceb, web (setup time) a[11:0] 5ns 2a d[15:0] 1b ceb, web to input invalid (hold time) a[11:0] 3 ns 2b d[15:0] 4 3 input rising to ceb, web falling ceb, web, oeb 5 (see note 1) ns 4 ceb, web rising to input falling ceb, web, oeb 5 (see note 1 , 2 ) ns 5 write access time (ceb, web to readyb) min = 1 tc, max = 4 tc 25 100 ns 6 ceb, web de-asserted to readyb de-asserted 9.4 ns 7a input valid to ceb, oeb (setup time) a[11:0] 5 ns 7b ceb, oeb to input invalid (hold time) a[11:0] 2 ns 8 input rising to ceb, oeb falling ceb, web, oeb 5 (see note 1) ns 9 ceb, oeb rising to input falling ceb, web, oeb 5 (see note 1) ns 10 read access time (ceb, oeb to readyb) min = 1.5 tc, max = 8 tc 37.5 200 ns 11a ceb, oeb asserted to signal asserted d[15:0] 4.0 8.4 ns 11b ceb, oeb de-asserted to signal de- asserted d[15:0] 3.8 8 ns 11c readyb 8.8 12 readyb, d skew 2 ns 13 ram_clk_testse rising to readyb falling use_ram_clk=1 3.7 13.5 ns 14 ram_clk_testse rising to readyb rising use_ram_clk=1 3 9.7 ns 15 ram_clk_testse rising to readyb deactivated 1->z use_ram_clk =1 ready delay=00 3.6 12.9 ns ready delay=01 4.5 15.4 ready delay=10 5.4 18.8 ready delay=11 6.4 22.2 16 read to read access inactivity time (ceb, oeb low to ceb, oeb low) min = 1.5 tc 37.5 (see note 1) ns
www.ams.com revision 1.0 11 - 20 AS8202B datasheet - detailed description notes: 1. prior to starting a read or write access, ceb, web and oeb have to be stable for at least 5 ns (see symbol 3, 4, 8, 9). in addition the designer has to consider the minimum inactivity time according to symbols 16, 17, 18, 19. for more information on the inactivit y times (see figure 3) . 2. to allow proper internal initialization, after finishing any write access (ceb or web is high) to the internal controller_o n register, ceb oeb and web have to be stable high within 200 ns (min = 8 tc). 3. all values not tested during production, guaranteed by design. figure 3. read/write access inactivity time 17 read to write access inactivity time (ceb, oeb low to ceb, web low) 5 (see note 1) ns 18 write to write access inactivity time (ceb, web low to ceb, web low) 5 (see note 1 , 2 ) ns 19 write to read access inactivity time (ceb, web low to ceb, oeb low) 5 (see note 1 , 2 ) ns table 5. asynchronous dpram interface symbol parameter conditions min typ max units ceb web oeb 16 read read 18 write 17 write 19 read
www.ams.com revision 1.0 12 - 20 AS8202B datasheet - detailed description figure 4. write access timing (ceb controlled) figure 5. write access timing (web controlled) figure 6. read access timing (ceb controlled) figure 7. read access timing (oeb controlled) 7.1.1 synchronous readyb generation figure 8. synchronous readyb timing synchronous readyb is aligned to host clock (with pulse duration of one host clock cycle) to fulfill the required host timing c onstraints for input setup and input hold time to/after host clock rising edge. note: connect use_ram_clk to vdd and ram_clk_testse to the host processor's bus clock to enable this mode of operation. due to possible metastability occurrence, it is not reco mmended to be used in safety critical systems. ceb web a valid valid d oeb readyb 1a 1b 2a 2b 3 6 5 4 ceb web a valid valid d oeb readyb 1a 1b 2a 2b 6 5 3 4 ceb web a valid d oeb readyb 7a 7b 8 11c 10 9 12 invalid valid 11a 11b ceb web a valid d oeb readyb 7a 7b 8 11c 10 9 12 invalid valid 11a 11b asynchronous readyb ram_clk_testse synchronous readyb 13 14 15
www.ams.com revision 1.0 13 - 20 AS8202B datasheet - detailed description 7.2 reset and oscillator 7.2.1 external reset signal to issue a reset of the chip t he resetb port has to be driven lo w for at least 1s. pulses unde r 50ns duration are discarded. a t power-up the reset must overlap the build-up time of the power supply. this re set may only be used if a proper power-on reset can be ensured (refer to section 7.2.2 integrated power-on reset ). 7.2.2 integrated power-on reset the device has an internal power-on-reset generator. when supply voltage ramps up, the internal reset signal is kept active (lo w) for 33s typical. note: in case of non-compliance keep t he external reset (resetb) active for min. 5 ms after supply volt age is valid and main clock is stable. 7.2.3 oscillator circuitry the main clock requires an external oscillator. the bus guardian requires an external oscillator or an external quartz. figure 9. main clock setup xin0 of the main clock shall be supplied by a 40mhz clock provided by an oscillator ic. table 6. pin mode pin name mode comment xin1 analog bus guardian oscillator input (external clock input) resetb in external reset table 7. parameters symbol parameter min typ max unit dv/dt supply voltage slope 551 - - v/ms tpores power on reset active time after vdd > 1,0v 25 33 49 s external oscillator 40mhz square wave xino
www.ams.com revision 1.0 14 - 20 AS8202B datasheet - detailed description figure 10. bus guardian clock setup the bus guardian clock (xin1/xout1) supports driving a quartz crys tal oscillation, as well as a clock input by an external osci llator. 7.2.4 built-in characteristics 7.3 ttp bus interface the AS8202B contains two ttp bus units, one for each ttp channel, building the ttp bus interface. each ttp bus channel contains a transmitter and a receiver and can be configured to be either in the asynchronous or synchronous mode of operation. note that t he two channels (channel 0 and channel 1) can be configured independently for either of these modes. the drivers of the txd and cts pins are actively driven only during a transmission window, all the other time the drivers are s witched off and the weak pull resistors are active. external pull resistors must be used to define the signal levels during idle phases. note: the transmission window may be different for each channel. table 8. characteristics symbol pin parameter min typ max unit note tosc_startup1 xin1/xout1 oscillator startup time (bus guardian clock) 20 ms frequency: 16mhz table 9. bus interface connections pin name tx inactive txd[0] weak pull-up cts[0] weak pull-down txd[1] weak pull-up cts[1] weak pull-down xin1 xout1 16 m hz rd rf cext cext xin1 xout1 16 m hz square wave external quartz external oscillator
www.ams.com revision 1.0 15 - 20 AS8202B datasheet - detailed description 7.4 ttp asynchronous bus interface when in asynchronous mode of operation the channel's bus unit uses a self-clocking transmission encoding which can be either mf m or manchester at a maximum data rate of 4 mbit/s on a shared media (physical bus). the pins can either be connected to drivers usi ng recessive/ dominant states on the wire as well as drivers using active push/pull functionality. the rxd signal uses '1' as the inactivity level. in the so-called rs485 compatible mode longer periods of '0' are treated as in activity. if the rs485 compatible mode is not used, the application must care to drive rxd to '1' during inactivity on the bus. 7.5 ttp synchronous bus interface when in synchronous mode of operation, the bus unit uses a synchronous transfer method to transfer data at a rate between 20 an d 25 mbit/s. the interface is designed to run at 25 mbit/s and to be fully compatible with the commercial 100 mbit/s ethernet mii (media ind ependent interface) according to ieee standard 802.3 (ethernet csma/cd). connecting the synchronous ttp bus unit to a 100 mbit/s ethernet ph y is done by connecting txd, cts, txclk, rxer, rxclk, rxdv a nd rxd of any channel to txd0txd0, txen, txclk, rxer, rxclk, rxdv and rxd0 of the phy's mii. the pins txd1, txd2 and txd3 of the phy's mii should be linked to vss. the signals rxd1, rxd2, rxd3, col and crs as well as the mmii (management interface) should be left open or can be used for diagnostic purposes by the application. note that the frames sent by the AS8202B are not ethernet compatible and that an ethernet hub (not a switch) can be used as a ' star coupler' for proper operation. also note that the ethernet phy must be co nfigured for full duplex operation (even though the hub does no t support full duplex), because ttp has its own collision management that should not interfere with the phy's half-duplex collision management . in general, the phy must not be configured for automatic configuration ('auto negotiation') but be hard-configured for 100 mbit/s, full dup lex operation. note: to run the interface at a rate other than 25 mbit/s other transceiver phy components have to be used. table 10. asynchronous bus interface connections pin name mode connect to phy note txd[0] out txd transmit data channel 0 cts[0] out cts transmit enable channel 0 txclk[0] in no function (do not connect) rxer[0] in no function (do not connect) rxclk[0] in no function (do not connect) rxdv[0] in no function (do not connect) rxd[0] in rxd receive data channel 0 txd[1] out txd transmit data channel 1 cts[1] out cts transmit enable channel 1 txclk[1] in no function (do not connect) rxer[1] in no function (do not connect) rxclk[1] in no function (do not connect) rxdv[1] in no function (do not connect) rxd[1] in rxd receive data channel 1 table 11. synchronous bus interface connections pin name mode connect to phy note txd[0] out txd0txd0 transmit data channel 0 cts[0] out txen transmit enable channel 0 txclk[0] in txclk transmit clock channel 0 rxer[0] in rxer receive error channel 0 rxclk[0] in rxclk receive clock channel 0 rxdv[0] in rxdv receive data valid channel 0
www.ams.com revision 1.0 16 - 20 AS8202B datasheet - detailed description 7.6 test interface the test interface supports the manufacturing test and characterization of the chip. in the application environment test pins h ave to be connected as following: ?? stest, ftest, fidis: connect to vss ?? ttest: connect to vdd 7.7 led signals the led port consists of three pins. via the medl each of these pins can be independently configured for any of the three modes of operation. at power-up and after reset the led port is inactive and only weak pull-down resistors are connected. after the controller is s witched on by the host and when it is processing its initialization, the led port is initialized to the selected mode of operation. each led pin can be configured to be either a push/pull driver (drives both low and high) or to be only an open-drain output (d rives only low). rxd[0] in rxd0 receive data channel 0 txd[1] out txd0 transmit data channel 1 cts[1] out txen transmit enable channel 1 txclk[1] in txclk transmit clock channel 1 rxer[1] in rxer receive error channel 1 rxclk[1] in rxclk receive clock channel 1 rxdv[1] in rxdv receive data valid channel 1 rxd[1] in rxd0 receive data channel 1 caution: any other connection of these pins may cause permanent damage to the device and to additional devices of the application. table 12. led signals pin name protocol mode timing mode bus guardian mode led2 rpv 1 or protocol activity 7 1. rpv is remote pin voting. rpv is a network-wide agreed signal used typically for agreed power-up or power-down of the applica tion's external drivers. time overflow 2 2. time overflow is active for one clock cycle at the event of an overflow of the internal 16-bit time counter. time tick is act ive for one clock cycle when the internal time is counted up. time overflow and time tick can be used to externally clone the internal time contr ol unit (tcu). with this information the application can precisely sample and trigger events, for example. action time 3 3. action time signals the start of a bus access cycle. led1 sync valid 4 4. the controller sets this output when cluster synchronization is achieved (after integration from the listen state, after ackn owledge in the coldstart state). time tick 2 bde1 5 5. bde0 and bde1 show the bus guardian's activity, '1' signals an activated transmitter gate on the respective channel. led0 protocol activity 6 or rpv 7 6. protocol activity is typically connected to an optical led. the flashing frequency and rhythm give a simple view to the inter nal ttp pro- tocol state. 7. led2's rpv mode and led0's protocol activity mode can be swapped with a medl parameter. microtick 8 8. microtick is the internal main clock signal. bde0 5 table 11. synchronous bus interface connections pin name mode connect to phy note
www.ams.com revision 1.0 17 - 20 AS8202B datasheet - package drawings and markings 8 package drawings and markings the product is available in a 80-pin lqfp package. figure 11. drawings and dimensions marking: yywwgzz. yy ww g zz @@ manufacturing year manufacturing week plant identifier traceability code sublot identifier as8202nfb ttp yywwgzz @@ licensed by
www.ams.com revision 1.0 18 - 20 AS8202B datasheet - package drawings and markings revision history note: typos may not be explicitly mentioned under revision history. revision date owner description 1.0 26 mar, 2013 hgl release of datasheet
www.ams.com revision 1.0 19 - 20 AS8202B datasheet - ordering information 9 ordering information note: all products are rohs compliant and ams green technical support is available at www.ams.com/technical-support for further information and requests, email us at sales@ams.com (or) find your local distributor at www.ams.com/distributor table 13. ordering information ordering code marking description delivery form package AS8202B-alqr as8202nfb ttp communication controller tray 80-pin lqfp
www.ams.com revision 1.0 20 - 20 AS8202B datasheet - ordering information copyrights copyright ? 1997-2013, ams ag, tobelbaderstrasse 30, 8141 unterpremstaetten, austria-europe. trademarks registered ?. all right s reserved. the material herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written con sent of the copyright owner. all products and companies mentioned are trademarks or registered trademarks of their respective companies. disclaimer devices sold by ams ag are covered by the warranty and patent indemnification provisions appearing in its term of sale. ams ag makes no warranty, express, statutory, implied, or by description rega rding the information set forth herein or regarding the freedom of the described devices from patent infringement. ams ag reserves the right to change specifications and prices at any time and without notice. therefore, prior to designing this product into a system, it is necessary to check with ams ag for current information. this product is intended for use in normal commercial applications. applications requiring extended temperature range, unusual environmental requirements, or high reliabi lity applications, such as military, medical life-support or life-sustaining equipment are specifically not recommended without addi tional processing by ams ag for each application. for shipments of less than 100 parts the manufacturing flow might show deviations from the stan dard production flow, such as test flow or test location. the information furnished here by ams ag is believed to be correct and accurate. however, ams ag shall not be liable to recipient or any third party for any damages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruptio n of business or indirect, special, incidental or consequential damages, of any kind, in connection with or arising out of the furnishing, perfo rmance or use of the technical data herein. no obligation or liability to recipient or any third party shall arise or flow out of ams ag rendering of technical or other services. contact information headquarters ams ag tobelbaderstrasse 30 a-8141 unterpremstaetten, austria tel : +43 (0) 3136 500 0 fax : +43 (0) 3136 525 01 for sales offices, distributors and representatives, please visit: http://www.ams.com/contact contact information headquarters tttech computertechnik ag. schoenbrunner strasse 7 a-1040 vienna, austria tel : +43 (1) 5853 434 0 fax : +43 (1) 5853 434 90 support@tttech.com www.tttech.com

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